Built upon the functionality and the capability of the 5000X (Greencreek) chipset, the SuperMicro X7DA8 Motherboard provides the performance and feature set required for dual processor-based servers with configuration options optimized for communications, presentation, storage, computation or database applications. The 5000X (Greencreek) chipset supports single or dual Xeon 64-bit dual core processor with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000X (Greencreek) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXH-V). The 5000X (Greencreek) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1.333 GHz data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3 GB/sec.) The MCH chipset connects up to 8 Fully Buffered DIMM modules, providing a total of 32.0 GB/s for DDR2 667/533 memory. The MCH chipset also provides three x8 PCI-Express and one x4 ESI interface to the ESB2. In addition, the 5000X (Greencreek) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.

Built upon the functionality and the capability of the 5000X (Greencreek) chipset, the SuperMicro X7DAE motherboard provides the performance and feature set required for dual processor-based servers with configuration options optimized for communications, presentation, storage, computation or database applications. The 5000X (Greencreek) chipset supports single or dual Xeon 64-bit dual core processor with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000X (Greencreek) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXH-V). The 5000X (Greencreek) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1.333 GHz data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3 GB/sec.) The MCH chipset connects up to 8 Fully Buffered DIMM modules, providing a total of 32.0 GB/s for DDR2 667/533 memory. The MCH chipset also provides three x8 PCI-Express and one x4 ESI interface to the ESB2. In addition, the 5000X (Greencreek) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.

Built upon the functionality and the capability of the 5000P (Blackford) chipset, the SuperMicro X7DB8 motherboard provides the performance and feature set required for dual processor-based servers with configuration options optimized for communications, presentation, storage, computation or database applications. The 5000P (Blackford) chipset supports single or dual Xeon 64-bit dual core processor(s) with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P (Blackford) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXH). The 5000P (Blackford) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333 MHz data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3GB/sec.). The MCH chipset connects up to eight Fully Buffered DIMM modules, providing a total memory bandwidth of up to 32.0 GB/s. The MCH chipset also provides one x8 PCI-Express and one x4 ESI interfaces to the ESB2. In addition, the 5000P (Blackford) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.

Built upon the functionality and the capability of the 5000P (Blackford) chipset, the SuperMicro X7DB8+ motherboard provides the performance and feature set required for dual processor-based servers with configuration options optimized for communications, presentation, storage, computation or database applications. The 5000P (Blackford) chipset supports a single or dual Intel 64-bit dual core processor(s) with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P (Blackford) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXH). The 5000P (Blackford) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333 MHz data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3GB/sec.) The MCH chipset connects up to 16 Fully Buffered DIMM modules, providing a total memory bandwidth of 25.5 GB/s for DDR2 533, and 32.0 GB/s for DDR2 667. The MCH chipset also provides three x8 PCI-Express and one x4 ESI interface to the ESB2. In addition, the 5000P (Blackford) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.

Built upon the functionality and the capability of the 5000P (Blackford) chipset, the SuperMicro X7DBE motherboard provides the performance and feature set required for dual processor-based servers with configuration options optimized for communications, presentation, storage, computation or database applications. The 5000P (Blackford) chipset supports single or dual Xeon 64-bit dual core processor(s) with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P (Blackford) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXH). The 5000P (Blackford) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333 MHz data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3GB/sec.). The MCH chipset connects up to eight Fully Buffered DIMM modules, providing a total memory bandwidth of up to 32.0 GB/s. The MCH chipset also provides one x8 PCI-Express and one x4 ESI interfaces to the ESB2. In addition, the 5000P (Blackford) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.

Built upon the functionality and the capability of the 5000P (Blackford) chipset, the SuperMicro X7DBE+ motherboard provides the performance and feature set required for dual processor-based servers with configuration options optimized for communications, presentation, storage, computation or database applications. The 5000P (Blackford) chipset supports a single or dual Intel 64-bit dual core processor(s) with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P (Blackford) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXH). The 5000P (Blackford) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333 MHz data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3GB/sec.) The MCH chipset connects up to 16 Fully Buffered DIMM modules, providing a total memory bandwidth of 25.5 GB/s for DDR2 533, and 32.0 GB/s for DDR2 667. The MCH chipset also provides three x8 PCI-Express and one x4 ESI interface to the ESB2. In addition, the 5000P (Blackford) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.